![]() Of course the processor does not send it, and as a result this slave just waits and waits. At this point, the slave will have put the next bit out on the SDA line (because the SCL line may have dropped to a low on reset) and awaits the next clock on SCL. An extraneous reset on the processor will generally create this condition, especially if the processor cannot save its status. The problem is that the master has forgotten where it was when it was interrupted or reset. The slave is still waiting to send the remainder of the data requested by the master. ![]() Initially this looks like a device problem, but it is not. The Analog Devices “ Implementing an I2C Reset” suggests :įrequently the master, which is usually a microcontroller or a gate array, will be interrupted in the middle of its communication with an I2C slave and, upon return, find a stuck bus. There are many scenarios when something like this can occur. The bus relies on orderly communication and if a device holds one of these lines low you’re in trouble. There are two “Bus Stuck” scenarios: either the SDA or SCL lines become held low. Each device has an address on the bus and will only speak when spoken to by the Master.įor the purposes of this article I shall just look at what can go wrong and how we might recover from it. With a potential multitude of devices hanging off this same bus, they must play nicely with each other, and in order to do this, there is often a Master and number of Slave devices. It is an incredibly useful interface and you can hang a multitude of very useful chips off just these two wires, for example Real-Time Clocks, EEPROM memories, Accelerometers, interface expands, etc. These should normally sit high at whatever voltage your system is running at ie 5V or 3V3. The i2c (Inter-IC Communication) Bus consists of 2 wires (hence often called Two-Wire Interface aka TWI when you want to avoid using the i2c licensed term) the Data (SDA) and Clock (SCL).
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